The semiconductor industry has achieved a steady increase of the integration density of semiconductor devices with integrated circuits. Also a rapid increase of the frequencies, at which circuit elements may be operated, has been achieved. Both developments have been enabled, among others, by the replacement of aluminum and aluminum alloys as conductive materials for interconnect elements by copper. Copper has a lower electric resistance than aluminum and aluminum alloys and is more resistant to electromigration than these materials.
The interconnect elements are typically arranged in a stacked layer architecture referred to as interconnect stack and form conductive lines, plugs, or vias of an interconnect network, according to the specific requirements of a particular integrated circuit. The interconnect elements of an interconnect stack are typically separated from each other by layers of a dielectric material.
The introduction of copper (Cu) in the fabrication of interconnect elements for integrated circuits requires barriers to prevent a diffusion of Cu from the interconnect element into a respective adjacent dielectric layer or into the semiconductor substrate. A diffusion of Cu would give rise to a rapid degradation of interconnect structures. This in turn affects the performance of active devices of an integrated circuit or leads to an early.
U.S. Pat. No. 6,339,025 B1 describes the fabrication of a capping layer as a diffusion barrier on a Cu interconnect element. In the described process flow, a copper interconnect element is provided that is laterally defined by lateral barrier layers preventing the diffusion of copper into a laterally surrounding dielectric layer. The structure is subjected to chemical mechanical polishing (CMP) to remove residual copper and barrier-layer material from the dielectric layer. On the exposed dielectric layer and the exposed interconnect elements, a silicon-rich silicon nitride layer is formed by plasma-enhanced chemical vapor deposition. In this step, silane and ammonium NH3 are used as precursors. A sufficiently high ratio of the flow rates of silane and ammonium leads to a high silicon content in the silicon nitride layer. This favors a reaction of the deposited silicon with copper and results in a copper silicide layer, which is formed between the exposed copper interconnect element and the silicon nitride layer. The copper silicide layer enhances the adhesion of the silicon-rich nitride layer, which forms the capping layer.
It has been observed that the SiN capping layer on top of the CuSi-layer built with such processing is often discontinuous in Cu-based interconnect elements with grains of different crystal orientations, resulting in a locally defective diffusion-barrier cap. This causes reliability problems such as undesired shortcuts in the interconnect stack and Cu-related deep defects in silicon, which lead to a corrupted device performance and a reduced device lifetime.